The present invention relates to a test method for nonvolatile memory devices.
In recent years, there has been an increasing demand for nonvolatile memory devices that can be electrically programmed and erased and do not need the refresh function of rewriting data at specific intervals.
The nonvolatile memory cell is an element enabling electrical program/erase operations and is configured to perform the program and erase operations by changing its threshold voltage as electrons are migrated by a strong electric field applied to a thin oxide layer.
A fabrication process of the nonvolatile memory device includes a test process for completed products. In particular, there has been known a multi-chip test method, which can reduce the test time and perform tests for several chips at the same time. In this multi-chip test method, it is necessary to minimize the test time.